1. Field of the Invention
The invention relates to the field of MOS electrically programmable read-only memories (EPROMs).
2. Prior Art
Numerous electrically programmable read-only memories (EPROMs) are commercially available. In many cases, these memories employ floating gate memory devices; the floating gates of which are charged from the substrate through avalanche injection or channel injection. In general, these memory arrays are erased by exposing them to ultraviolet radiation. Examples of floating gate memory cells and memories are described in U.S. Pat. Nos. 3,996,657; 4,094,012; 4,114,255; and 4,142,926.
In a typical layout of these floating gate memory devices or cells, the cells are arranged in pairs. Each cell pair is connected to an overlying metal line through a metal contact. Thus, one-half contact per cell is required. These contacts require a relatively large amount of substrate area and thus are one limitation on the fabrication of higher density arrays. Moreover, these metal contacts decrease the production yields of the memories since they are generally more difficult to fabricate than other semiconductor elements in the array. As will be seen, the present invention eliminates most of these metal contacts, and by way of example, employs one metal contact per sixteen cells.
Some of the initial steps used in the presently described process are similar to the initial steps used in the fabrication of a mask programmed read-only memory as described in co-pending application, Ser. No. 907,557, filed May 19, 1978 and entitled "MOS DOUBLE POLYSILICON READ-ONLY MEMORY AND CELL", assigned to the assignee of the present application. Other related mask programmed read-only memory structures are described in U.S. Pat. No. 4,095,251.